This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-095401, filed on Mar. 31, 2003, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and column selecting and testing methods of the device. More particularly, the invention is concerned with a semiconductor memory device which can sequentially access the m sense amplifiers (m=1, 2, . . . n) among n sense amplifiers (n is a natural number) connected to one data input/output line, in time series, without specifying from the outside of the device.
2. Description of the Related Art
Recently, in a high-speed and highly integrated semiconductor memory device, as the wiring resistance and contact resistance caused by shrinkage increase, the resistance of the elements tends to increase. Conversely, the device operating speed tends to increase as the transistor operating speed increases. Particularly, in DRAM (Dynamic Random Access Memory), there is a problem of an insufficient data writing error caused by the resistance on the route of accessing a memory cell (e.g., refer to xe2x80x9cDRAM scaling-down 0.1 xcexcm generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plugxe2x80x9d, Beom-Jun, Jin et al, Symposium on VLSI Technology. Digest of Technical Papers, pp. 127-128, and xe2x80x9cA 6.25 ns random access 0.25 xcexcm embedded DRAMxe2x80x9d, DeMone, P. et al, Simposium on VLSI Circuits Digest of Technical Papers, 2001, pp. 237-240).
Generally, a highly integrated semiconductor memory device employs redundancy technology to replace a defective cell with a redundant cell. Even for the above-mentioned cell with defective-resistance (hereinafter, referred to as a high resistance cell), usually, a replacement method using a spare row or column cell is adopted. However, in addition to a decrease of yield due to the cell""s own defect, the yield will also be decreased by replacing a high-resistance cell by a spare cell. Further, in most cases, a high-resistance cell is found only by a high speed test, and is difficult to be found by a test using a low speed tester that is usually used for detection of defects. Moreover, there is a problem that a high resistance cell will become defective even if a test is performed with a high speed tester after packaging.
Further, in order for a semiconductor memory device to cover an increase in the required memory capacity and delay in the latency of memory cells, in recent semiconductor memory devices, it is often demanded to sequentially access a plurality of sense amplifiers connected to the same data input/output line, in time series, without specifying from outside the device.
FIG. 12 shows a configuration of the essential parts of a semiconductor memory device (e.g., DRAM) for which the above-mentioned operation is demanded. In FIG. 12, a reference numeral 101 denotes a memory cell. One memory cell 101 stores 1-bit cell data. In this example, each memory cell 101 is connected to one of multiple word lines WL [j] (j=0, . . . , jxe2x88x921) and one of eight bit lines BL [i] (i=0, . . . ,7). The bit lines BL [0] to BL [7] are connected to eight sense amplifiers 102 (102a to 102h). Reading and writing the cell data for each memory cell 101 are performed through each sense amplifier 102a to 102h. 
The reference numerals 103a and 103b denote a sense amplifier writing/reading circuit. The sense amplifier writing/reading circuit 103a is connected to an external data input/output line DIa/DOa (an external data input line DIa/external data output line DOa) and an internal data line DQa. The sense amplifier writing/reading circuit 103b is connected to an external data input/output line DIb/DOb (an external data input line DIb/external data output line DOb) and an internal data line DQb. In this example, one internal data line DQa is connected to four sense amplifiers 102a to 102d through a column selection gate 104. The other internal data line DQb is connected to four sense amplifiers 102e to 102h through a column selection gate 104. Namely, among the eight sense amplifiers 102a to 102h, the four sense amplifiers 102a to 102d connected to the bit lines BL [0] to BL [3] are connected commonly to the same external data input/output lines DIa and DOa. Similarly, the four sense amplifiers 102e to 102h connected to the bit lines BL [4] to BL [7] are commonly connected to the same external data input/output lines DIb/DOb.
The column selection gate 104 includes eight NMOS transistors. Among these eight NMOS transistors, the drains of four NMOS transistors are connected to the bit lines BL [0] to BL [3]. Each source is commonly connected to one internal data line DQa, and the gates are connected to the column selection lines CSL [0] to CSL [3]. Similarly, the drains of the other four NMOS transistors are connected to the bit lines BL [4] to BL [7], and each source is commonly connected to the other internal data line DQb, and the gates are connected to the column selection lines CSL [0] to CSL [3], respectively.
A reference numeral 105 denotes a column selector circuit. The column selector circuit 105 selects one of the column selection lines CSL [0] to CSL [3] on the time series according to a clock signal CLKC and a control signal.
FIG. 13 shows one memory cell taken out of the above-mentioned DRAM. The above-mentioned bit line BL [i] and the above-mentioned internal data lines DQa/DQb are actually complementary. For example, as shown in FIG. 13, the bit line BL [0] consists of bit lines BLt [0] and BLc [0] (or, BLt/c [0]). The internal data line DQa consists of internal data lines DQta and DQca (or, DQt/ca).
The memory cell 101 is connected to one of the bit line BLt [0] and bit line BLc [0]. (In this example, the memory cell 101 is connected to the bit line BLt [0].) The memory cell 101 has a cell transistor 101-1 and a cell capacitor 101-2. The cell transistor 101-1 is an NMOS transistor, whose source is connected to the bit line BLt [0] and the gate is connected to the word line WL [j], respectively. The drain of the NMOS transistor is connected to one end of the cell capacitor 101-2, and functions as a storage node (SN). The other end of the cell capacitor 101-2 is connected to a fixed potential (VPL). Writing the cell data is realized by storing electric charges in the cell capacitor 101-2. For the electric charge holding characteristic of the cell capacitor 101-2, a negative fixed voltage (VBB) is usually applied to the back bias terminal of the cell transistor 101-1.
The sense amplifier 102a is connected to the bit lines BLt [0] and BLc [0], respectively. As a sense amplifier 102a, for example, a dynamic latch type circuit is used.
The column selection gate 104 includes two NMOS transistors, whose drains are connected to the bit lines BLt [0] and BLc [0]. Each gate is commonly connected to the column selection line CSL [0], and the sources are connected to the internal data lines DQta and DQca, respectively. The internal data lines DQta and DQca are connected to the above-mentioned sense amplifier writing/reading circuit 103a, as shown in FIG. 12.
FIG. 14 shows the operation of the DRAM configured as mentioned above. CLK is an operation clock necessary for operating the DRAM. COM is a command signal supplied from an external device. A read command (R) or a write command (W) is inputted at a certain timing. Here, description will be given on the case where the write command (W) is inputted. A row address to activate is also inputted, but it is omitted here. BLt/c [0] and BLt/c [3] are signal waveforms of the bit lines BLt [0], BLc [0] and bit lines BLt [3], BLc [3], when the memory cell is connected to the bit lines BLc [0] and BLt [3]. The signal amplitude (swing width) of the bit line BL [i] is VBLH potential (about 1.5V in the current generation). VSN is a potential of a storage node SN of each memory cell 101.
When the command signal COM is entered, the word line WL [j] corresponding to the address is activated. For example, assuming that the word line WL is activated, the cell data of the corresponding memory cell 101 will be outputted to the bit line BLc [0] and BLt [3]. In this example, the cell data xe2x80x9c0xe2x80x9d is read out to the both. When the cell data is read out to each BLc [0] and BLt [3], the sense amplifier 102 is activated. Thus, the potential of the bit lines BLt/c [0] and BLt/c [3] is amplified. Thereafter, synchronizing with the operation clock CLK, the column selection lines CSL [0], CSL [1], CSL [2] and CSL [3] will be sequentially activated. During this period, the potential of the internal data line DQa varies as indicated by D0 to D3, corresponding to the potential D0 to D3 of the external data input line DIa.
In this state, first, the column selection line CSL [0] is activated. Then, the amplified potential of the bit line BLt/c [0] is inverted, and the cell data xe2x80x9c1xe2x80x9d is written in the memory cell 101. At this time, the potential of the bit line BLc [0] quickly becomes close to the VBLH potential. However, the potential VSN of the storage node SN requires much time to become the VBLH potential, because of the contact resistance of the cell transistor 101-1 and bit line BLt/c [0], and the resistance caused by junctions in the route to the storage node SN. A dotted line indicates the potential VSN of the storage node SN, when a normal cell is used. A chain line indicates the potential VSN of the storage node SN when a high-resistance cell with a higher resistance than that of a normal cell is used.
After the column selection lines CSL [1] and CSL [2] are sequentially activated, the column selection line CSL [3] is activated last. Then, the amplified potential of the bit line BLt/c [3] is inverted, and the cell data xe2x80x9c1xe2x80x9d is written in the memory cell 101. At this time, the potential of the bit line BLt [3] quickly becomes close to the VBLH potential.
Leaving time for data-writing, the word line WL and sense amplifier 102 are deactivated. Then, the bit lines BLt/c [0] and BLt/c [3] are equalized (about the potential of VBLH/2) to prepare for the next reading operation. When the word line WL is deactivated, a rise in the potential of the storage node SN is suppressed.
Since the column selection line CSL [0] is activated at an early time, the potential VSN of the storage node SN becomes sufficiently close to the VBLH potential, and the memory cell 101 connected to the bit line BLc [0] rarely becomes a defective cell, even if it is a high-resistance cell. Contrarily, as to the memory cell 101 connected to the bit line BLt [3], the time from activation of the column selection line CSL [3] to deactivation of the word line WL is short, and the potential VSN written in the storage node SN is likely to become short. Especially, in a high-resistance cell, the potential VSN of the storage node SN is further decreased, and the cell easily becomes defective because of the pause characteristic or the time to the next access and the noise during reading.
As in a high resistance cell, a cell with defective-resistance which fails due to an insufficient data writing error, caused by the insufficient potential of the storage node SN, is replaced by a spare row or column cell.
As explained above, in the prior art, when a cell that is defective in resistance is to be replaced by a row or column spare cell, a problem arises in a test, and a yield decreases.
According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of memory cells to store data; k data input/output lines (k=a natural number); a plurality of sense amplifiers which are provided in n number (n=a natural number) for the k data input/output lines, and perform reading and writing cell data for the plurality of memory cells; a column selection gate which selects one sense amplifier among the n sense amplifiers, and connects the selected sense amplifier to the corresponding data input/output line; a selector circuit which controls the column selection gate, and sequentially selects m sense amplifiers (m=1, 2, . . . , n) among the n sense amplifiers; and a switching circuit which changes the order of selecting the m sense amplifiers by the selector circuit.
According to a second aspect of the present invention, there is provided a column selecting circuit comprising: a plurality of memory cells to store data; k data input/output lines (k=a natural number); a plurality of sense amplifiers which are provided in n number (n=a natural number) for the k data input/output lines, and perform reading and writing cell data for the plurality of memory cells; a column selection gate which selects one sense amplifier among the n number of sense amplifiers, and connects the selected sense amplifier to the corresponding data input/output line; a selector circuit which controls the column selection gate, and sequentially selects m sense amplifiers (m=1, 2, . . . , n) among the n sense amplifiers; and a switching circuit which changes the order of selecting the m sense amplifiers by the selector circuit; wherein the order of selecting columns by the selector circuit is changed according to a reset value signal from the switching circuit.
According to a third aspect of the present invention, there is provided a method of testing a semiconductor memory device comprising: a plurality of memory cells to store data; k data input/output lines (k=a natural number); a plurality of sense amplifiers which are provided in n number (n=a natural number) for the k data input/output lines, and perform reading and writing cell data for the plurality of memory cells; a column selection gate which selects one sense amplifier among the n number of sense amplifiers, and connects the selected sense amplifier to the corresponding data input/output line; a selector circuit which controls the column selection gate, and sequentially selects m sense amplifiers (m=1, 2, . . . n) among the n sense amplifiers; and a setting circuit which sets the order of selecting the m sense amplifiers by the selector circuit; wherein whether a high-resistance cell with higher resistance than that of a normal cell can be prevented from becoming defective, is tested by changing the order of selecting columns by the selector circuit, according to the set value of the setting circuit.